The present invention relates to addressing and accessing a ROM in a data processing system. More particularly, the invention facilitates addressing a ROM having a number of storage addresses greater than the address output capacity of a processor and its coupled address bus. The invention has particular, but not exclusive, applicability to the field of vehicle diagnostics equipment.
Read Only Memories (ROMs) traditionally have been used in data processing systems for storing executable code. Accessing such data from the ROM permits the processor to perform its own operating functions as well as to interact with various peripheral devices. Executable code stored in ROM also can be used by the processor to perform any of various applications to which the system may be dedicated. ROM data typically are permanently stored to be accessed as needed in accordance with read enable and address signals output by the processor. ROM data are not normally overwritten or erased. In contrast, data generated by the processor are stored temporarily in random access memory for further manipulation by the processor or for storage in a more permanent storage medium, such as magnetic or optical disc or tape.
A simplified block diagram of a conventional processor-ROM arrangement is shown in FIG. 1. Processor 10 has a plurality of address output terminals A0-An at for outputting an address signal to address bus 12 for accessing data in the ROM 20. Address signals are received at the address bus input of the ROM and fed to ROM address decoder 22. The address decoder identifies that portion of the ROM data storage to be accessed in accordance with the received address. Data are accessed in response to a read enable signal generated by the processor, received at an appropriate input of the ROM (not illustrated). The accessed data are output to data bus 14, which is connected to data input terminals D0-Dm at the processor. The address bus and data bus each contain a number of individual lines equal, respectively, to the number of processor terminals to which it is connected. Each line carries a single bit signal. Data are typically accessed in eight bit (one byte) increments, each ROM address identifying a byte of data storage. Data bus 14 thus is made up of eight lines connected to eight data terminals at the processor.
The number of lines in address bus 12 limits the number of addresses that can be applied to ROM 20 and thus conventionally is correlated to the storage capacity of the ROM. For example, if ROM 20 contains one megabyte of storage, an address bus of at least twenty bits would be needed to directly address and access the entire storage. If address bus 12 and processor address terminals provide a fewer number of bits, for example, a sixteen bit bus, only a fraction of the ROM storage capacity can be directly accessed from the addresses received at the ROM input from the address bus. To accommodate full usage of the ROM, modification of the internal ROM control circuit would be necessary so that an address received from the address bus can be used to appropriately identify one of a plurality of storage locations assigned to the address. In addition to the circuit complexity introduced by such accommodation, modification of the processor would be required to provide appropriate control signals for operation in a plurality of address modes. Loss of operating speed is an additional negative byproduct.
Design of a system can take into account the size of the ROM component and match the address bus to permit direct access to all ROM data storage locations, as in the above described example of providing a twenty bit address bus for a one megabyte ROM. As technology evolves and develops, however, the need for increased ROM storage capacity, beyond the capacity of the address bus of an existing system becomes more commonplace. Factors such as development of new applications and upgrades of original applications for the system may dictate a requirement for ROM expansion.
For example, the system may be part of a dedicated diagnostic device in which such new applications and upgrades are furnished with additional ROM executable code, for use such as in vehicle diagnostics. Computerized units for engine analysis, wheel alignment, etc., are provided with inputs coupled from a vehicle, as well as user input. Such units include displays for waveforms and other graphical representation of measured vehicle parameters. These units may be linked with portable computerized devices for use by technicians. Diagnostic applications are appended with detailed text explanation and graphic information, such as pictorial diagrams, for display at a system monitor. Stored text messages for display may include instructions for set up and use of the instrument, a compilation of help messages, etc. The text and graphic information is represented by extensive strings of data in ROM storage for recurrent access in dependence upon the application context. Typically, as applications are further refined, data are added thereafter. While the original one megabyte ROM chip can be replaced with one or more updated ROM chips and appended with additional ROM chips for text and graphic storage, replacement of the address bus and modification of the processor is not usually a practicable matter.
With the number of ROM address inputs limited to the size of the processor address bus, various methods have been employed, alluded to above, for mapping an address received at the ROM input to one of a plurality of ROM storage locations. A conventional approach is memory page switching, with attendant disadvantages of added ROM control circuit complexity, processor operation modifications, and loss of access speed.
The need thus exists for directly accessing ROM storage locations in which the cumulative number of addresses, and thus the number of ROM address input terminals, exceeds the address capacity of the processor and address bus. Such a solution should provide advantages with respect to the conventional arrangements with respect to circuit modification complexities and access speed.
The present invention fulfills the aforementioned needs. An advantage of the present invention is that a ROM is provided with sufficient input address terminals for receipt of a unique address for each data storage location, even though the number of ROM input addresses exceeds the capacity of the processor and address bus.
An additional advantage of the present invention is that a dual mode of ROM read address operations is provided without modification of ROM circuitry for accessing address locations greater in number than the capacity of the address bus. This aspect of the invention offers the further advantage of providing a random address mode for randomly accessing the ROM and a sequential address mode for accessing sequentially stored data strings at a high access rate.
These and other advantages are satisfied, at least in part, by allocating bus addresses to each of the modes in the following manner. A first portion of the bus addresses is allocated as random reading mode bus addresses for randomly addressing the ROM for reading data, the bus addresses having direct correspondence with ROM addresses. Other bus addresses are allocated as sequential reading mode bus addresses for addressing the ROM in sequential ROM address order for reading data. Successive output by the processor of the same sequential reading mode bus address effects application to the ROM of sequentially numbered ROM addresses. In this manner a data stream can be accessed from the ROM at a high speed. The first numbered address of the plurality of the sequential ROM address string is loaded as data into at least one counter. Processor output of the sequential reading mode address effectuates application of the contents of the counter as an address to the ROM and increments the counter so that a successive output of the same address by the processor effectuates application of the incremented counter contents as an address to the ROM.
The first address of the string is loaded into the counter in response to generation of a write enable signal by the processor and output to the address bus of the sequential reading mode bus address. A decoder, having an input connected to the address bus and an output connected to the counter, is set to identify the associated sequential mode address at the address bus. Detection of the sequential mode address results in application of an activation signal from the decoder to the counter for loading the address data from the processor via the data bus to the counter input. The counter may comprise a plurality of interconnected stages, each loaded with data representing a portion of the address, whereby the aggregate number of bits carried by the counter is made equal to the number of ROM address bits and exceeds the number of processor address bus bits. Each stage of the counter may be linked with a separate decoder and thus individually loaded in response to output to the processor address bus of a respective one of the sequential reading mode bus addresses.
In both the random access mode and the sequential mode, addresses are applied to ROM address input terminals by a multiplexer having a number of output terminals equal to the number of ROM address input terminals. The multiplexer has input terminals connected to the address bus and each of the counter stages. The decoder provides detection of the mode of reading operation on the basis of whether the address output by the processor can be decoded to produce a change in output state of the decoder. Through appropriate logic circuitry connected to the decoder, a read control signal, indicative of the mode of reading operation, is applied to the multiplexer to apply the received bus address signal as a ROM address to the ROM in the random access reading mode or the outputs of the decoder stages as a ROM address to the ROM in the sequential access reading mode.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.